FD DAQ Multiplicity
Revision as of 22:38, 4 January 2016 by BrettViren (talk | contribs) (Created page with "= Electronics = Not DAQ, but: * 16 ch input to analog ASIC (FE + ADC), 8:1 digital MUX, 2 channel digital output * 8 ASIC / analog mother board * 8 analog mother boards / FE...")
Electronics
Not DAQ, but:
- 16 ch input to analog ASIC (FE + ADC), 8:1 digital MUX, 2 channel digital output
- 8 ASIC / analog mother board
- 8 analog mother boards / FEMB assembly
- 128 analog channels / FEMB assembly
- 1 digital ASIC, 16 channel input, 4:1 MUX, 4 channel output (each 1Gbps)
- 2Mhz at 12 bits is 24 Mbps
- 16ch*24Mbps*8MUX = 3072Mbps into digital ASIC, (up to 4Gbps out on 4 links)
- 20 FEMB assembly / APA
- 150 APA / 10kt
- 128:4 total channel MUX
DAQ
1 DAQ Rack holding/servicing
- 1 cryo flange
- 2 APA
- 2 COB (16 RCE)
- 1 BRC (Board reader computer) 3 NICs (RCE network, SSP network, detector network)
- 2 internal switches (one for RCE, one for SSP) 10Gbps?
2 APA can make 6144 Mbps
Refs
- CDR figure 4.14 and 4.15
- [http://lbne2-docdb.fnal.gov:8080/cgi-bin/RetrieveFile?docid=10889&filename=DUNE_DAQOverview_TechReview_Barrv5.pdf&version=6 Overview of
Data Acquisition page 7] presentation by Giles Barr.
- LAr TPC DAQ page 12 presentation by Matt Graham.
